(A Conventional Integrator)
FIG. 10 shows a conventional integrator 100. The integrator 100 generally uses a switched capacitor circuit and an operational amplifier 101. The switched capacitor circuit is inserted between an input terminal supplied with an input voltage Vin and the operational amplifier 101. The switched capacitor circuit is configured of a switch S101, a capacitor CS, and a switch S102. The switch S101 connects either one of the input terminal supplied with the input voltage Vin and the ground to one end of the capacitor CS. The switch S102 connects the other end of the capacitor CS to either one of an inverting input end (−) of the operational amplifier 101 and the ground. A positive input end (+) of the operational amplifier 101 is connected to the ground, and a negative feedback capacitor CF is inserted between an output end where Vout appears and the inverting input end (−).
Next, the operation of the conventional integrator 100 is described. First, the switch S101 selects the input terminal, and the switch S102 selects the ground. In the capacitor CS, charges QS (=VinCS) are accumulated. In the next phase, the switch S101 selects the ground, and the switch S102 selects the inverting input end of the operational amplifier 101.
When the gain of the operational amplifier 101 is sufficiently large and establishes a virtual ground, the entire charges QS accumulated in the capacitor CS are transferred to and accumulated in the capacitor CF, where integrating operation is performed. A relation between an output voltage Vout [n] of the integrator 100 at an n-th clock and an output voltage Vout [n−1] of the integrator 100 at an (n−1)-th clock is represented by the following equation (P1).Vout[n]=Vout[n−1]+(CS/CF)Vin[n]  (P1)When the clock advances in this manner, the output voltage Vout has a value obtained by integrating the input voltage Vin.
However, because a negative feedback technology is used as described above in the conventional integrator 100, the operation disadvantageously becomes unstable when the clock frequency is increased, and thus the operation highly depends upon clock frequency. As a result, there was a difficulty in stable high-speed operation.
(A Conventional Operational Amplifier)
An example of the circuit structure of a conventional operational amplifier 110 is shown in FIG. 11. The conventional operational amplifier 110 has a bias current source 111 configured so as to let a constant current IB flow toward the ground, letting the current IB in total flow through N-type transistors M111 and M112 configuring the paired differential transistors for biasing. A positive input voltage Vin_p is applied to the gate voltage of the N-type transistor M111, and an inverting input voltage Vin_n is applied to the gate voltage of the N-type transistor M112. P-type transistors M113 and M114 are configured to provide a current mirror to perform active loads, with their sources connected in common to a power supply voltage VDD and drains connected to the drains of the N-type transistors M111 and M112, respectively. The output voltage Vout appears at a terminal to which the drain of the P-type transistor M114 and the drain of the N-type transistor M112 are commonly connected.
Next, the operation of the conventional operational amplifier 110 is described. With the current IB in total let flow through the N-type transistors M111 and M112 configuring paired differential transistors for biasing, an input voltage difference (Vin_p−Vin_n) is amplified to appear at the output end Vout. The output end Vout is closer to VDD if the voltage Vin_p is higher than the voltage Vin_n and otherwise the output end Vout is closer to the ground potential.
In the integrator with the above-described conventional operational amplifier 110, it is known that a gain bandwidth GBW is required to be in the order of twice as large as a clock frequency fclk for operating a switched capacitor circuit. When the bias current is IB and the load capacitor of the output end is CL, the gain bandwidth GBW is represented by the following equation (P2).GBW=gm/(2πCL)≈(IB/Veff)/(2πCL)  (P2)Here, Veff is an effective gate voltage, and is given by Veff=VGS−VT, where VGS is a source to gate voltage and VT is a threshold voltage.
In the integrator 100 with the above-described operational amplifier 110, operation with variable clock frequency is desired. However, this is difficult with the conventional integrator, because a necessary GBW cannot be achieved and the integrator cannot operate appropriately unless the bias current IB is proportional to the clock frequency fclk. Since changes in the bias current IB renders changes in the bias point, it is difficult to adjust the bias current IB for a large extent. Even if the necessary GBW could be achieved at a low clock frequency, it is difficult to greatly decrease the current, posing another problem of a greater power consumption.
(A Conventional Delta Sigma A/D Converter)
The integrator 100 can be incorporated in, for example, a delta sigma A/D converter 120 shown in FIG. 12. The delta sigma A/D converter 120 is configured to have a plurality of integrators arranged in several stages connected to a comparator 124. The integrators are a first integrator 121, a second integrator 122, . . . , an n-th integrator 123 (each integrator has the same internal structure). The delta sigma A/D converter 120 has a comparison output Dout fed back to an input stage. In this configuration, the voltage of the first integrator 121 at the time of charge transfer is switched to VREF+ or VREF− by a switch S103.
The above-described delta sigma A/D converter 120 has a signal-to-noise ratio (SNR) indicating its performance represented by the following equation (P3).SNR=(3/2)((2L+1)/π2L)(2N−1)2·M2L+1  (P3)Here, L is the number of steps of the integrator, N is the number of quantization bits of the comparator, and M is an oversampling ratio. When an input signal frequency is fin and a sampling frequency is fs, the oversampling ratio M is represented by the following equation (P4).M=fs/(2fin)  (P4)
Even if the number of steps of the integrator and the number of quantization bits of the comparator are not changed, by setting the oversampling ratio M, the SNR can be variable. To obtain the same SNR for various input signal frequencies fin, the sampling frequency fs is made proportional to the input signal frequency fin. However, as described above, it is difficult for the conventional integrator 100 to make the operating frequency variable and optimize power consumption, and it is thus difficult to make the sampling frequency of the delta sigma A/D converter variable and optimize power consumption (refer to Japanese Laid-Open Patent Application Publication No. H05-37300).